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mar2010
- 基于FPGA的单精度浮点数乘法器设计，本文设计了一个基于FPGA的单精度浮点数乘法器。乘法器为五级流水线结构。设计中采用了改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构，减少了部分积的数目，缩短了部分积累加的耗时；提出了对尾数定点乘法运算中Wallace树产生的2个伪和采用部分相加的处理方式，有效地提高了的运算速度；并且加入了对特殊值的处理模块，完善了乘法器的功能。单精度浮点数乘法器在Altera DE2开发板上进行了验证，其在Cyclone II EP2C35F672C6器
pingpangqiu
- 本文使用 FPGA 芯片来模拟实际的乒乓球游戏。本设计是基于 Altera 公司的 FPGA Cyclone II 芯片 EP2C5T144C8 的基础上实现，运用 Verilog HDL 语言编程，在 Quartus II 软件上进行编译、仿真，最终在开发板上成功实现下载和调试。 -This article uses the FPGA chip to simulate the actual game of table tennis. The design is based Altera
two-way-Elevator
- 基于Altera Quartus的双向电梯程序，可以烧制进入Cyclone 的FPGA中进行硬件调试。-Based on the Altera Quartus two-way lift procedures, firing into the Cyclone FPGA hardware debugging.
DecodeHexabc
- Decoder 8bits FPGA for cyclone altera DE2-70
cyclone_lcd_controller
- Altera 公司的cyclone II板子的LCD板子驱动程序-LCD driver for cyclone II of Altera company
20130607UART
- 读取温度传感器DS18B20数据并通过串口发送到上位机。程序开发是基于altera 的EP2C8Q208芯片。-Read the temperature sensor DS18B20 data and sent it to the host computer via the serial port. The program development is based on the the altera s cyclone II device :EP2C8Q208.
LCD_test
- this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
FT245BL_test
- this a example for the mouse vga for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
CD1_MT9M111_DISPALY
- 使用Altera fpga cyclone III系列EP3C16对摄像头MT9D001的驱动，并可以在VGA显示器上实时显示。使用quartus 10.0打开，注意不要使用中文路径。-Using Altera fpga cyclone III series EP3C16 MT9D001 the camera driver, and can be displayed in real time on a VGA monitor. Using quartus 10.0 open, be carefu
br-soc-fpga
- cyclone v的altera公司的带arm硬核的soc设计指南-cyclone v the product of altera with the arm hard process cores introductiong
EX4V1.1
- 该设计是基于Verilog HDL的秒表。此设计是在Altera的Cyclone II系列的FPGA上验证过了。能够实现精确计时。-This design is a stopwatch based on the Verilog HDL. And it has been verified on the platform of Cyclone II s FPGA of Altera. Finally it can achieve accurate timing.
DDS_Core_HSpeed_ADDA_C5H
- 基于FPGA的高速ADDA采集工程源代码，是基于ALTERA公司的CycloneⅡ芯片的工程示例。-FPGA-based high-speed ADDA acquisition project source code is an example of ALTERA engineering based company CycloneⅡ chips.
DM5_VGA_img_C5H
- 基于FPGA的VGA输入采集工程示例，是基于ALTERA公司的CycloneⅡ的EP2C5芯片，具有一定的参考价值。-VGA input sample collection project based FPGA is based on the company s CycloneⅡ of EP2C5 ALTERA chip, has a certain reference value.
DDS_Core_Norml_ADDA_C5H
- 基于FPGA的DDS内核的信号采集和输出，是基于ALTERA公司的CycloneⅡ的EP2C5芯片，是一个很好的参考示例。-DDS core FPGA-based signal acquisition and output is based on the company s CycloneⅡ of EP2C5 ALTERA chip, is a good reference example.
PS2_SOC1
- 用Verilog 设计了PS2 键盘 模块。 在altera公司的Cyclone系列测试了。 正常动作。包含者 doc软件，说明了动作原理。-This is a state-machine driven serial-to-parallel and parallel-to-serial interface to the ps2 style keyboard interface.
PS2_SOC2
- 利用Verilog HDL设计了PS2鼠标。 我们在Altera公司的Cyclone开发平台上测试了这个模块。正常动作，可以直接利用。-This is a state-machine driven serial-to-parallel and parallel-to-serial interface to the ps2 style mouse.
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
hex7segb
- Implimentation of the switches and 7 segment display bit counter on an Altera DE2 baord via VHDL code on the Cyclone II FPGA
cyclone_ivProgramming-Guide
- 本应用笔记提供了一组简单易用的指南和一列在Cyclone® IV 设计中需要考虑的因素。 Altera 建议在设计过程中遵循本应用笔记中介绍的指南-This application note provides a set of simple and easy to use guidelines and a list of needs to be considered in the Cyclone IV design factors. Altera is recommended t
DE0_development_board_cd_data
- 这是DE0开发板的光盘资料，是友晶公司的关于altera公司的Cyclone III开发板。-This is DE0 development board disc material, is friend chip of altera company Cyclone III development board.